Pci Express Mini Card Pin Assignment

PCI Express Card

PinSymbolTypeLegend
1gnd
2usb d-I/OUSB Data
3usb d+I/OUSB Data
4cp usb#OCard use USB bus
5rsvd0Reserved
6rsvd1Reserved
7smb clkSM Bus Clock
8smb dataSM Bus Data
91.5 volt
101.5 volt
11wake#OWake up main CPU from card
123.3 Volt auxProvided when main CPU is off (support for WAKE)
13pe rst#IPower Good (reset)
143.3 Volt
153.3 volt
16clk req#OClock Request - enable ICS9DB106
17cp pe#OCard us PCI Express bus
18refclk-IClock input from buffer ICS9DB106
19refclk+IClock input from buffer ICS9DB106
20gnd
21PERn0IPCI Express RX -
22PERp0IPCI Express RX +
23gnd
24PETn0OPCI Express TX -
25PETp0OPCI Express TX +
26gnd
  • Verified with Congatec design

PCI Express - 1-lane slot

PinSymbolTypeLegend
a01PRSNT#1Hot-Plug presence detect
a02+12V
a03+12V
a04gnd
a05jtag2JTAG - Clock
a06jtag3JTAG - Data In
a07jtag4JTAG - Data Out
a08jtag5JTAG - Mode Select
a093.3 Volt
a103.3 Volt
a11PERST#IPower Good (Reset)
a12gnd
a13refclk+IClock input from buffer ICS9DB106
a14refclk-IClock input from buffer ICS9DB106
a15gnd
a16PERp0IPCI Express RX +
a17PERn0IPCI Express RX -
a18gnd
b01+12V
b02+12V
b03rsvd0Reserved
b04gnd
b05smb clkSM Bus Clock
b06smb dataSM Bus Data
b07gnd
b083.3 Volt
b09jtag1JTAG - Reset
b103.3 Volt auxProvided when main CPU is off (support for WAKE)
b11wake#OWake up main CPU from card
b12rsvd1Reserved
b13gnd
b14PETp0OPCI Express TX +
b15PETn0OPCI Express TX -
b16gnd
b17PRSNT#2Hot-Plug presence detect
b18gnd
  • Verified with PCI Express official specification

PCI Express Mini Card

RowPinSymbolTypeLegendStatus
01WAKE#
03COEX1Function is OEM specificchanged
05COEX2Function is OEM specificchanged
07CLKREQ#ORequest to ICS9DB106 for clock signal, MiniCard can tie to ground. USB-only cards leave this open.
09Gnd
011REFCLK-IClock input from buffer ICS9DB106
013REFCLK+IClock input from buffer ICS9DB106
015Gnd
017ReservedReserved for future SIM Card pin C8
019ReservedReserved for future SIM Card pin C4
021Gnd
023PERn0IPCI Express RX -
025PERp0IPCI Express RX +
027Gnd
029Gnd
031PETn0OPCI Express TX -
033PETp0OPCI Express TX +
035Gnd
037Gndchanged
0393.3Vauxchanged
0413.3Vauxchanged
043Gndchanged
045Reserved
047Reserved
049Reserved
051Reserved
123.3 Vauxchanged
14Gnd
161.5 Volt
18UIM PWROSIM Card
110UIM_DATAI/OSIM Card
112UIM_CLKOSIM Card
114UIM_RESETOSIM Card
116UIM_VPPOSIM Card
118Gnd
120W_DISABLE#IWireless disable (active low)changed
122PERST#IPower Good (Reset)
1243.3Vaux
126Gnd
1281.5Volt
130SMB CLKISM Bus Clock
132SMB DataI/OSM Bus Data
134Gnd
136USB_D-I/OUSB Data
138USB_D+I/OUSB Data
140Gnd
142LED_WWAN#OActive low, max 9mA
144LED_WLAN#OActive low, max 9mA
146LED_WPAN#OActive low, max 9mA
1481.5Volt
150Gnd
1523.3Vauxchanged
  • Verified with PCI Express™ Mini Card Electromechanical Specification, 1.0, with ECN

PCI Express Cards - Compare Electrical Interfaces

SignalExpressCardExpress SlotExpress MiniTypeLegend
PERn0YesYesYesIPCI Express RX -
PERp0YesYesYesIPCI Express RX +
PERST#YesYesYesIReset (Power Good)
PETn0YesYesYesOPCI Express TX -
PETp0YesYesYesOPCI Express TX +
refclk-YesYesYesIClock input from buffer ICS9DB106
refclk+YesYesYesIClock input from buffer ICS9DB106
smb clkYesYesYesISM Bus Clock
smb dataYesYesYesI/OSM Bus Data
wake#YesYesYesOWake up main CPU from card
CLKREQ#YesYesOClock Request - enable ICS9DB106
usb d-YesYesI/OUSB Data
usb d+YesYesI/OUSB Data
cp pe#YesOCard us PCI Express bus
cp usb#YesOCard use USB bus
COEX1YesFunction is OEM specific
COEX2YesFunction is OEM specific
LED_WLAN#YesOActive low, max 9mA
LED_WPAN#YesOActive low, max 9mA
LED_WWAN#YesOActive low, max 9mA
UIM PWRYesOSIM Card
UIM_CLKYesOSIM Card
UIM_DATAYesI/OSIM Card
UIM_RESETYesOSIM Card
UIM_VPPYesOSIM Card
W_DISABLE#YesIWireless disable (active low)
PRSNT#1YesIHot-Plug presence detect
PRSNT#2YesOHot-Plug presence detect
jtag1YesIJTAG - Reset
jtag2YesIJTAG - Clock
jtag3YesIJTAG - Data In
jtag4YesOJTAG - Data Out
jtag5YesIJTAG - Mode Select
+12VYespwrPower 12 Volt
1.5 VoltYesYespwrPower 1.5 Volt
3.3 VoltYesYespwrPower 3.3 Volt
3.3 Volt auxYesYesYespwrPower 3.3 Volt, also present if main CPU is off, support for WAKE#
GNDYesYesYespwrGround

References

Category:Buses Connectors

Specifications

Specification TitleSpec RevDocument TypeRelease Date
Errata for the PCI Express® Base Specification Revision 3.1, Single Root I/O Virtualization and Sharing Revision 1.1, Address Translation and Sharing Revision 1.1, and M.2 Specification Revision 1.0
Final Release against Base Revision 3.1a.Subsequent ...view moreFinal Release against Base Revision 3.1a.Subsequent Errata will be against Base Revision 4.0 show less
3.x Errata
PCIe Link Activation ECN
Link Activation allows software to temporarily disab...view moreLink Activation allows software to temporarily disable Link power management, enabling the avoidance of the architecturally mandated stall for software-initiated L1 Substate exits. show less
4.x ECN
PCI Code and ID Assignment Specification, Revision 1.10 1.x Specification
Add a Second PCIe Lane to Type 1216 SDIO Based LGA Module ECN
The M.2 Type 1216 Land Grid Array (LGA) Connectivity...view moreThe M.2 Type 1216 Land Grid Array (LGA) Connectivity module is modified to add a second PCIe lane. Referring to Figure 99 on page 127 show less
1.x ECN
Additional Voltage Value for PWR_1 Rail V0.3 ECN
This proposal adds an additional voltage value to th...view moreThis proposal adds an additional voltage value to the PWR_1 rail in the PCIe BGA SSD 11.5x13 ECR. Table 3 of section 3.4 in the document “PCIe BGA SSD 11.5x13 ECR”, defines the PWR_1 signal as a 3.3V source. This is changed to now also include a 2.5V rail. show less
1.x ECN
_DSM Additions for Runtime Device Power Management
This ECN adds two capabilities by way of adding func...view moreThis ECN adds two capabilities by way of adding functions to the PCI Firmware Spec defined _DSM definition. show less
3.x ECN
OCuLink Wiring Chart ECN (Clean)
a....view morea. The connector and cable assembly pinout tables have been revised to show the complete OCuLink pinout assignments in all cases. b. The two left-most columns in the cable pinout tables have been combined for clarity. c. Due to the fact that the pinout tables span multiple pages, P1/P2 designations have been included in the appropriate column titles of the cable pinout tables to make it easier to follow which end of the cable is being addressed on each page in each table.  show less
1.x ECN
OCuLink BP Type ECN (Change Bar)
The backplane type (BP Type) signal was incompletely...view moreThe backplane type (BP Type) signal was incompletely specified in the original OCuLink 1.0 specification. Table 2-2 now includes a Type of logic used for this signal. A definition is provided for the logic levels of this signal. show less
1.x ECN
OCuLink Wiring Chart ECN (Change Bar)
a....view morea. The connector and cable assembly pinout tables have been revised to show the complete OCuLink pinout assignments in all cases. b. The two left-most columns in the cable pinout tables have been combined for clarity. c. Due to the fact that the pinout tables span multiple pages, P1/P2 designations have been included in the appropriate column titles of the cable pinout tables to make it easier to follow which end of the cable is being addressed on each page in each table. show less
1.x ECN
OCuLink BP Type ECN (Clean)
The backplane type (BP Type) signal was incompletely...view moreThe backplane type (BP Type) signal was incompletely specified in the original OCuLink 1.0 specification. Table 2-2 now includes a Type of logic used for this signal. A definition is provided for the logic levels of this signal.  show less
1.x ECN
PCI Express® Base Specification Revision 4.0, Version 1.0
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
4.x Specification
PCI Express® Base Specification Revision 4.0, Version 1.0 (Change Bar)
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. show less
4.x Specification
Native PCIe Enclosure Management ECN
Defines mechanisms for simple storage enclosure mana...view moreDefines mechanisms for simple storage enclosure management for NVMe SSDs, consistent with established capabilities in the storage ecosystem, with the first version of this capability defining a register interface for LED control. This ECN defines a new PCI Express extended capability called Native PCIe Enclosure Management (NPEM). show less
3.x ECN
Expansion ROM Validation ECN
Provide an optional mechanism to indicate to softwar...view moreProvide an optional mechanism to indicate to software the results of a hardware validation of Expansion ROM contents. show less
3.x ECN
PCI Code and ID Assignment Specification Revision 1.9
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications show less
1.x Specification
OCuLink CPRSNT# Notice ECN
The cable presence (CPRSNT#) signal was incompletely...view moreThe cable presence (CPRSNT#) signal was incompletely and inaccurately specified in the original OCuLink 1.0 specification. The definition for the logic levels of this signal contradicted the active low naming convention. The direction has multiple contradictions. show less
1.x ECN
PCIe CEM Thermal Reporting ECN
This ECN specifies changes to the PCI Local Bus Spec...view moreThis ECN specifies changes to the PCI Local Bus Specification Revision 3.0 and the PCI Express CEM Specification 3.0. Changes to the PCI Local Bus Specification cover a new VPD encoding and a 32-bit field. Changes to the PCI Express CEM Specification cover a series of graphs used to classify air flow impedance and thermal properties under varying conditions as well as the test figure and process to create these graphs for a given adapter add-in card. Adapter add-in card types supported by this include all SINGLE-SLOT and DUAL-SLOT PCIe CEM adapter add-in cards without integrated air movers, including standard height adapter add-in cards as well as low-profile adapter add-in cards). Adapter add-in cards with an integrated air mover were not addressed due to the added complication of their integrated air mover in the overall platform’s potential cooling redundancy. show less
3.x ECN
Hierarchy ID Message ECN
Defines a new, optional PCI-SIG Defined Type 1 Vendo...view moreDefines a new, optional PCI-SIG Defined Type 1 Vendor Defined Message. This message provides software and/or firmware, running on a Function, additional information to uniquely identify that Function, within a large system or a collection of systems. When a single system contains multiple PCI Express Hierarchies, this message tells a Function which Hierarchy it resides in. This value, in conjunction with the Routing ID number uniquely identifies a Function within that system. In clustered system, this message can include a System Globally Unique Identifier (System GUID) for each system. This value, in conjunction with the Hierarchy ID and Routing ID uniquely identifies a Function within that cluster. show less
3.x ECN
Enable PCIe and USB 3.1 Gen1 on M.2 Card Key B ECN
M.2 Key B (WWAN) is modified to enable PCIe and USB ...view moreM.2 Key B (WWAN) is modified to enable PCIe and USB 3.1 Gen1 signals to be simultaneously present on the connector. This enables support for a single SKU M.2 card that supports both PCIe and USB 3.1 Gen1. There are two implementation options enabled: 1. State #14 in the “Socket 2 Add-in Card Configuration Table” is re-defined to indicate an Add-in Card built to the PCI Express M.2 Specification, Revision 1.1 or later where both PCIe and USB 3.1 Gen1 are both present on the connector. The choice of Port Configuration is vendor defined. This enables the host to unambiguously determine that PCIe and USB 3.1 Gen1 are present on the connector. 2. States #4, 5, 6, 7 in the “Socket 2 Add-in Card Configuration Table” are re-defined to indicate that in addition to USB 3.1 Gen1, PCIe may be present on the connector. This definition was used by M.2 cards built to the PCI Express M.2 Specification, Revision 1.0 (USB 3.1 Gen1 on connector; PCIe is “no connect”). This definition is now also permitted to be used by M.2 cards built to PCI Express M.2 Specification, Revision 1.1 or later to indicate that PCIe and USB 3.1 Gen1 are both present on the connector. This allows GPIO port configurations to remain consistent with all other existing states. show less
1.x ECN
Flattening Portal Bridge (FPB) ECN
This ECR is intended to address a class of issues wi...view moreThis ECR is intended to address a class of issues with PCI/PCIe architecture that relate to resource allocation inefficiency. To explain this, first we must define some terms: Static use cases, refer to scenarios where resources are allocated at system boot and then typically not changed again Dynamic use cases, refer to scenarios where run-time resource rebalancing (allocation of new resources, freeing of resources no longer needed) is required, due to hot add/remove, or by other needs. In the Static cases there are limits on the size of hierarchies and number of Endpoints due to the Bus & Device Number “waste” caused by the PCI/PCIe architectural definition for Switches, and by the requirement that Downstream Ports associate an entire Bus Number with their Link. This proposal addresses this class of problems by “flattening” the use of Routing IDs so that Switches and Downstream Ports are able to make more efficient use of the available space. show less
3.x ECN
PCIe BGA SSD 11.5x13 ECN
This proposal adds a new 11.5 mm x 13 mm PCIe BGA SS...view moreThis proposal adds a new 11.5 mm x 13 mm PCIe BGA SSD form factor to the M.2 v1.1 specification.  show less
1.x ECN
OCuLink Skew
A PCI Express Receiver is required to tolerate 6 ns ...view moreA PCI Express Receiver is required to tolerate 6 ns of lane to lane skew when operating at 8.0 GT/s. The PCI Express OCuLink Specification allowed the cable assembly to consume the entire budget. The Transmitter and traces routing to the OCuLink connector need some of this budget. The PCI Express Card Electromechanical Specification Revision 3.0 assigns 1.6 ns to the total interconnect lane to lane skew budget. show less
1.x ECN
PCI Express® Mini Card Electromechanical Specification Revision 2.1
This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification 5 does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. show less
2.x Specification
PCI Express® Mini Card Electromechanical Specification Revision 2.1 with Change Bar
This specification defines an implementation for sma...view moreThis specification defines an implementation for small form factor PCI Express cards. The specification uses a qualified subset of the same signal protocol, electrical definitions, and configuration definitions as the PCI Express Base Specification, Revision 2.0. Where this specification 5 does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs. show less
2.x Specification
OCuLink Memory Map Change
This is a modification of the cable assembly memory ...view moreThis is a modification of the cable assembly memory map defined in OCuLink 1.0, Appendix A. The addresses for the data bytes contained within the external cable assembly's memory will be reorganized. In addition, some data in these fields are modified. show less
1.x ECN
OCuLink Server Change
Table 6-12 and Table 6-13 in Section 6.9 are modifie...view moreTable 6-12 and Table 6-13 in Section 6.9 are modified to reflect connector requirements for server/datacenter segment. In addition, this proposal also reflects a clarification in the Introduction text, Section 1 to include the server/datacenter market segment. show less
1.x ECN
PCI Express M.2 Specification Revision 1.1
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini 3 Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in 4 both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and 5 higher integration of functions onto a single form factor module solution. show less
1.x Specification
PCI Express M.2 Specification Revision 1.1 with Change Bar
The M.2 form factor is intended for Mobile Adapters....view moreThe M.2 form factor is intended for Mobile Adapters. The M.2 is a natural transition from the Mini 3 Card and Half-Mini Card (refer to the PCI Express Mini CEM Specification) to a smaller form factor in 4 both size and volume. The M.2 is a family of form factors that enables expansion, contraction, and 5 higher integration of functions onto a single form factor module solution. show less
1.x Specification
Errata for the PCI Express® OCuLink Specification Revision 1.0 1.x Errata
PCI Code and ID Assignment Specification Revision 1.8
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. show less
1.x Specification
PCI Code and ID Assignment Specification Revision 1.8 (Change Bar)
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. show less
1.x Specification
VF Resizable BARs ECN
Similar to, and based on, the Resizable BAR and Expa...view moreSimilar to, and based on, the Resizable BAR and Expanded Resizable BAR ECNs, this optional ECN adds a capability for PFs to be able to resize their VF BARs. This ECN is written with the expectation that the Expanded Resizable BAR ECN will have been released prior to this ECN’s release. This ECN supports all of the BAR sizes defined by both the Resizable BAR and Expanded Resizable BAR ECNs. show less
3.x ECN
SR-IOV Table Updates ECN
Update SR-IOV specification to reflect current PCI C...view moreUpdate SR-IOV specification to reflect current PCI Code and ID Assignment Specification, regarding PCI capabilities and PCI-E extended capabilities. Clarify the requirements for VFs regarding the other Capabilities added by ECNs that should have updated the SR-IOV specification but did not. show less
3.x ECN
Extended Message Data for MSI ECN
MSI is enhanced to include an Extended Message Data ...view moreMSI is enhanced to include an Extended Message Data Field for the function generating the interrupt. The MSI Capability Structure is modified to enable the new feature to be enabled/disabled; and a new Extended Message Data Field to be configured. This change only applies to MSI and not MSI-X. show less
3.x ECN
Expanded Resizable BARs ECN
The Resizable BAR capability currently allows BARs o...view moreThe Resizable BAR capability currently allows BARs of up to 512 GB (239), which allows address bits <38:0> to be passed into an Endpoint. This proposal extends resizable BARs to up to 263 bits, which supports the entire address space. show less
3.x ECN
Errata for the PCI Express® Base Specification Revision 3.1, Single Root I/O Virtualization and Sharing Revision 1.1, Address Translation and Sharing Revision 1.1, and M.2 Specification Revision 1.0 3.x Errata
M.2 SSIC Eye Limits Definition ECN
Definition of electrical eye limits (Eye Height and ...view moreDefinition of electrical eye limits (Eye Height and Eye Width) at the M.2 connector for SSIC host and device transmitter is proposed to be added in the specification. show less
3.x ECN
Root Complex Integrated Endpoints and IOV Updates
This ECN implements a variety of spec modifications ...view moreThis ECN implements a variety of spec modifications intended to correct inconsistencies related to, and to support more consistent implementation of, Root Complex integrated Endpoints, with a particular focus on issues relating to Single Root IO Virtualization (SR-IOV). show less
3.x ECN
PCI Express Base Specification Revision 3.1a with Change Bar
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.  show less
3.x Specification
PCI Express Base Specification Revision 3.1a
This specification describes the PCI Express® archit...view moreThis specification describes the PCI Express® architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification.  show less
3.x Specification
Emergency Power Reduction Mechanism with PWRBRK Signal ECN
This ECN defines two sets of related changes to supp...view moreThis ECN defines two sets of related changes to support an Emergency Power Reduction mechanism and to provide software visibility for this mechanism: 1. The Card Electromechanical Specification is updated to define an optional Emergency Power Reduction mechanism using RSVD pin B30. 2. The PCI Express Base Specification is updated to define an optional mechanism to indicate support for Emergency Power Reduction and to provide visibility as to the power reduction status of a Device. show less
3.x ECN
Supporting PCIe and SATA BGA form factor for SSDs ECN
This ECN is intended to define a new form-factor and...view moreThis ECN is intended to define a new form-factor and electrical pinout to the M.2 family. This proposal will allow PCIe and SATA to be delivered using a BGA package, expanding the use of the PCIe and SATA protocols in small form-factor applications. The new BGA pinout content is based on the Socket 3 Key-M definitions. BGA pinout supports additional pins than defined for Socket-3, for soldered-down form-factors. show less
1.x ECN
PCI Express® OCuLink Specification Revision 1.0
This document is a companion Specification to the PC...view moreThis document is a companion Specification to the PCI Express Base Specification and other PCI Express® 2 documents listed in Section 1.1. The primary focus of the PCI Express OCuLink Specification is the implementation 3 of internal and external small form factor PCI Express® connectors and cables optimized for the client and mobile 4 market segments. This Specification discusses cabling and connector requirements to meet the 8.0 GT/s signaling 5 needs in the PCI Express Base Specification. 6 No assumptions are made regarding the implementation of PCI Express compliant components on either side of 7 the Link; such components are addressed in other PCI Express Specifications. show less
1.x Specification
Designated Vendor-Specific Extended Capability ECN
Define a Vendor-Specific Extended Capability that is...view moreDefine a Vendor-Specific Extended Capability that is not tied to the Vendor ID of the Component 5 or Function. This capability includes a Vendor ID that determines the interpretation of the remainder of the capability. It is otherwise similar to the existing Vendor-Specific Extended Capability. show less
3.x ECN
PCI Code and ID Assignment Specification Revision 1.7
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. show less
1.x Specification
PCI Code and ID Assignment Specification Revision 1.7 with change bar
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. show less
1.x Specification
WWAN Key C Definition
This ECR describes the necessary changes to enable a...view moreThis ECR describes the necessary changes to enable a new WWAN Key C definition to be included as an addition to the existing spec. The intent is to create a dedicated WWAN socket Key and pinout definition. This new pinout definition will be focused on WWAN specific interfaces and needs.  show less
1.x ECN
PCI Code and Assignment Specification Revision 1.6
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. show less
1.x Specification
PCI Code and Assignment Specification Revision 1.6 with Change Bar
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. show less
1.x Specification
M.2 2242 WWAN Module
Add 2242 form factor for WWAN modules using Socket 2...view moreAdd 2242 form factor for WWAN modules using Socket 2 with key B. show less
1.x ECN
Errata for the PCI Express Base Specification Revision 3.0 3.x Errata
Power-up requirements for PCIe side bands in a Vbat powered system
In ECN “Power-up requirements for PCIe side bands (P...view moreIn ECN “Power-up requirements for PCIe side bands (PERST#, etc.)” - submitted by Dave Landsman and Ramdas Kachare - section 3.1.3.2.1 is redefined to provide a more realistic timing model for reset. show less
1.x ECN
Tx Blanking and SYSCLK on Socket 1 Related Pinouts
The proposed change is to include 2 GNSS Aiding sign...view moreThe proposed change is to include 2 GNSS Aiding signals, that we already have allocated in the Type 1216 pinout, to the Socket 1 Key E pinout and Type 2226/3026 pinout. Due to lack of free pins in the Key E pinout, it is proposed to define 2 SDIO Input signals as dual functional pins. They would be defined with their original SDIO functionality along with and alternate GNSS Aiding signals functionality to enable a GNSS solution on Type 2230 solutions on Socket 1 Key E solutions. The GNSS signals to be added are the Tx Blanking and SYSCLK signals and it is suggested to overlay them on the SDIO RESET# and SDIO CLK respectively which are also inputs. In this way it is less likely to cause a potential contention.  show less
1.x ECN
M.2 COEX Signal Definition - UART
Definition of two of the three COEX pins as a UART T...view moreDefinition of two of the three COEX pins as a UART Tx/Rx communication path between Socket 1 and Socket 2 in favor of WWAN ßà Connectivity coexistence. The intent is to definitively define the location of the source and sink sides of the signal path.  show less
1.x ECN
Transition of NFC Signals from 3.3V to 1.8V
The proposed change is to change the current voltage...view moreThe proposed change is to change the current voltage level of the NFC related signals (I2C DATA, I2C CLK and ALERT#) on the Connectivity pinouts and definitions from 3.3V to 1.8V signal level to better align with future platforms operating signal levels typical in the industry.  show less
1.x ECN
Extension Devices
Provide specification for Physical Layer protocol aw...view moreProvide specification for Physical Layer protocol aware Retimers for PCI Express 3.0/3.1. show less
3.x ECN
Power-up requirements for PCIe side bands (PERST#, etc.)
Section 3.1.3.2.1 is redefined to provide a more rea...view moreSection 3.1.3.2.1 is redefined to provide a more realistic timing model for reset. show less
1.x ECN
M.2 Signal Definition – Audio & ANTCTL Functions
Definition of the four Audio pins to provide definit...view moreDefinition of the four Audio pins to provide definitive functions assigned to each pin of the Audio interface. show less
1.x ECN
SMBus interface for SSD Socket 2 and Socket 3
SMBus interface signals are included in sections 3.2...view moreSMBus interface signals are included in sections 3.2 and 3.3 and related minor clarifications added to sections 1.2, 1.3, 2.2, 4.1, 4.2, 5.2.2, and 5.3. show less
1.x ECN
Add USB 3.0 to the Mini Card
Mobile broadband peak data rates continue to increas...view moreMobile broadband peak data rates continue to increase. With LTE category 5, USB 2.0 will not meet the performance requirements. LTE category 5 peak data rates are 320 Mbps downlink; 75 Mbps uplink. Most USB 2.0 implementations achieve a maximum of about 240 Mbps throughput. Looking longer term, the ITU has set a target of 1 Gbits/s for low mobility applications for IMT Advanced. show less
2.x ECN
NOP DLLP
This ECN accomplishes two housekeeping tasks associa...view moreThis ECN accomplishes two housekeeping tasks associated with DLLP encoding. show less
3.x ECN
Separate Refclk Independent SSC Architecture (SRIS) JTOL and SSC Profile Requirements
Modifies specifications to provide revised JTOL curv...view moreModifies specifications to provide revised JTOL curve for SRIS mode and provides additional frequency domain constraint of SSC profile jitter on reference clocks. show less
3.x ECN
PCI Code and Assignment Specification Revision 1.5 with Change Bar
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. show less
1.x Specification
PCI Code and Assignment Specification Revision 1.5
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. show less
1.x Specification
Tighten Mini Card Power Rail Voltage Tolerance
Modify the Mini Card specification to tighten the po...view moreModify the Mini Card specification to tighten the power rail voltage tolerance. show less
2.x ECN
PLL Bandwidth Test Limits
Modifies the limits used by the PLL bandwidth test t...view moreModifies the limits used by the PLL bandwidth test to allow guardband for a single PLL test solution to be used at PCI-SIG compliance workshops without impacting pass/fail results for member companies. show less
3.x ECN
PCI Express M.2 Specification Revision 1.0
The M.2 form factor is used for Mobile Add-In cards....view moreThe M.2 form factor is used for Mobile Add-In cards. The M.2 is a natural transition from the Mini Card and Half-Mini Card to a smaller form factor in both size and volume. The M.2 is a family of form factors that will enable expansion, contraction, and higher integration of functions onto a single form factor module solution. show less
1.x Specification
PCI Code and Assignment Specification Revision 1.4
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. show less
1.x Specification
PCI Code and Assignment Specification Revision 1.4 with Change Bar
This specification contains the Class Code and Capab...view moreThis specification contains the Class Code and Capability ID descriptions originally contained the PCI Local Bus Specification, bringing them into a standalone document that is easier to reference and maintain. This specification also consolidates Extended Capability ID assignments from the PCI Express Base Specification and various other PCI specifications. show less
1.x Specification
Readiness Notifications (RN)
 Defines mechanisms to reduce the time software need...view more Defines mechanisms to reduce the time software needs to wait before issuing a Configuration Request to a PCIe Function or RC-integrated PCI Function following power on, reset, or power state transitions. show less
3.x ECN
PCI Express Card Electromechanical Specification Revision 3.0
This specification is a companion for the PCI Expres...view moreThis specification is a companion for the PCI Express Base Specification, Revision 3.0. Its primary focus is the implementation of an evolutionary strategy with the current PCI™ desktop/server mechanical and electrical specifications. Access Test Channel S-Parameters. show less
3.x Specification

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